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Many processors include I²C or SPI interfaces. Others, such as 8051 processors
and their derivatives
, support multiplexed address and data buses. Timekeeping NV RAMs use the same control signals as SRAMs, to which many processors provide an easy interface, and include battery-backed RAM in various densities.
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Reading and writing the time and date registers is an asynchronous event, separate from the automatic update of the internal registers. Two types of read errors can occur when the time and date registers increment while being read. First, the data could change while a single register is being read, or, second, the data could change during the time between reading two registers. Assume, for example, that the clock increments from 11:59:59 to 12:00:00 during a read of the seconds, minutes, and hours registers. The time read could be 12:00:59, which is incorrect.
